In the manufacture of semiconductor devices, especially on advanced nodes, multiple lithographic layer stacks and multiple lithographic exposure and etch sequences are required for forming vias and connecting lines in the Back End Of Line (BEOL).
A typical sequence for the formation of such connecting lines is described in Kobayashi, Shinji, et al. “Analyzing block placement errors in SADP patterning.” Proc. Of SPIE Vol 9779, 2016. This sequence starts by forming a pattern of spacer-defined trenches, followed by providing a lithographic stack and performing a first lithographic exposure and etch sequence to form blocks above portions of the trenches. Subsequently, the trench pattern is etched deeper into the substrate, such as into a hard mask layer in the substrate, whereby the blocks define interruptions in the trenches.
Once the wished interrupted trench pattern is transferred in the hard mask, in order to form vias, it is typical to use a second lithographic stack and a second lithographic exposure and etch sequence to pattern vias into the hard mask. After both the via and trench patterns have been etched to the depth in the dielectric underlying the hard mask, the corresponding openings may be filled with a conductive metal to form the vias and connecting lines. A flowchart of this process up to the etching in the dielectric is shown in FIG. 8.
There still exists a need for more straightforward BEOL methods.